Hardware and Integration


PathForward Vendor: Intel

Principal Investigators: Hal Finkel, lead, Argonne National Laboratory; Ian Karlin, Lawrence Livermore National Laboratory

Objectives and Planned Approach:

The challenges in reaching exascale computing are well documented; the most common of these are power, reliability and resiliency, cost, and usability. Intel® Federal LLC’s approach to achieve the Department of Energy’s (DOE’s) PathForward goals leverage the Intel state-of-the-art technology as well as strengthen the entire Intel Architecture (IA) ecosystem for HPC. The work packages in the PathForward SOW address challenges in diverse areas of energy efficiency, fabric costs, memory and high-speed IO, performance, scalability and usability. Planned approaches include evolving the many-core architecture to focus on application acceleration and on-chip specialization resulting in exceptional energy efficiency, performance/$, and performance/watt. Closer integration of various node and system resources will also be used to reduce latencies and increase usable fabric at lower costs and lower power. Finally optimized communication architectures and scalable, highly-distributed storage designs based on non-volatile memory will be used to offer new capabilities necessary for the scale and performance expected on an exascale system.