Hardware and Integration

PathForward

PathForward Vendor: HPE

Principal Investigator: Robin Goldstone, Lawrence Livermore National Laboratory

The objective and customers

The HPE PathForward project accelerates technologies to improve application performance and developer productivity, while maximizing energy efficiency and reliability of an exascale system. It improves the competitiveness of exascale system proposals, where application performance figures of merit will be the most important criteria, and not theoretical peak. It also improves confidence in the value and feasibility of advanced technology options to build an exascale system in the 2021-2023 timeframe. Finally, it identifies the most promising technology options that are expected to reach maturity in time for the design of the next generation exascale systems. To achieve these objectives, HPE expects to focus on the system architecture and the integration technologies that can deliver an exascale system in a node-agnostic way. The customers for the resulting Exascale system are the NNSA and Office of Science labs who intend to acquire a leadership system in the 2021-2023 timeframe.

The planned approach

The key to a productive exascale machine lies in maintaining balance across the entire system, without excessively relying on a single individual compute node technology, which is expected to go through disruptive changes in the next five years. The planned approach builds upon HPE foundational technology investments, and tunes and accelerates them towards the HPC applications relevant to the DOE Labs customers.  The targeted exascale design leverages the investments in The Machine research program, such as the novel “memory semantics” fabric that can simplify system design and programming by harmonizing communication and data access over a new, fast, efficient and open network protocol called Gen-Z. The memory semantics model of Gen-Z simplifies application programming, unifies compute and storage traffic, and can enable new shared-memory programming models, when appropriate. The Gen-Z fabric is at the foundation of the HPE’s exascale approach.

The project is organized in the following five workpackages (WP):

  • WP1 (System Design) includes the design of the platform architecture, the system management, the power and cooling. It also develops functional prototypes as proof-of-concept, evaluation platforms, and co-design testbeds in collaboration with DoE Labs.
  • WP2 (Compute Node Design) includes the development of a foundational Gen-Z chipset. The chipset will be validated in the prototype to show its viability for an exascale design.
  • WP3 (Data Movement) includes the R&D activities to study and advance the Gen-Z interconnect, such as building a multi-ported Gen-Z, researching the best topologies, and developing the simulation tools to evaluate the different options.
  • WP4 (Optical Interconnects) advances the design and manufacturing of silicon photonics and VCSEL-based optics, with special emphasis on the 3D packaging and direct-to-chip fiber attachment. Photonics is a core technology to reach the energy and cost efficiency needed by exascale systems
  • WP5 (IO Node Design) includes studying exascale storage architecture, and developing foundational technologies, and component prototypes, to enable a variety of fabric-attached media devices, ranging from DRAM and SSD, to next-generation storage-class memory.

The end state

The resulting exascale design aims to achieve a far more balanced system as measured by key system metrics, and thus greater sustained performance than current HPC systems. The foundational technologies will be proven and integrated in working prototypes to reduce risk, and identify the next step towards productization.